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dual 2 mhz, 800 ma, synchronous, low quiescent current buck regulator data sheet adp2230 features input voltage range: 2.3 v to 6.5 v fixed and ad justable output voltage options fixed output voltage pair options: 1.2 v/1.8 v, 1.2 v/3.3 v, 1.8 v/3.3 v ad justable output voltage range: 0.8 v to 6 v minimum guaranteed continuous output current: 800 ma up to 94% efficiency low quiescent current of 15 a for both channels in power saving mode ( psm ) low shutdown current: 0.1 a (typical) 100% d uty c ycle for low dropout operation sync p in switching f requency options 2 mhz fixed pulse - width modulation ( pwm ) mode 2 mhz psm/ pwm automatic transitioning mode external clock synchronization from 1.5 mhz to 2.5 mhz enable input with precision thresholds for each output 180 phase shifted pwm outputs for minimum v in ripple current - limit and thermal shutdown (tsd) protection qui ck output discharge (qod) 10 - lead , 3 mm 3 mm 0.75 mm lfcsp package applications portable and battery - powered equipment automatic meter readers (wsn) point of sales and transaction processing instruments mobile phones digital camera s and audio devices medical instruments medium format display tablets and pads general description the a dp2230 include s two high efficiency, low quiescent current, 800 ma, step - down, d c - to - dc converters in a small, 10 - lead, 3 mm 3 mm, lfcsp package. the total solution requires only five tiny external components. when the adp2230 is used with three 0603 capacitors and two 2 mm 2 mm inductors, the total solution size is about 48 mm 2 , resulting in the smallest footprint solution to meet a variety of portable applications. the adp2230 buck regulator use s a proprietary, high speed, current mode, constant frequency, pwm control scheme for excellent stability and transient response. the buck outputs operate out of phase to reduce the input current ripple. to ensure the longest battery life in portable applications, the adp2230 ha s a power saving variable frequency mode that reduces the switching frequency under light load conditions. typical application circuit figure 1 . fixed output voltage typical application circuit during logic controlled shutdown, the input is disconnected from the output , and it draws less than 0.1 a from the input source. the adp2230 operate s from input voltages from 2.3 v to 6.5 v , allowing the use of multiple alkaline, nimh, or lithium cells and other standard power sources. the adp2230 offer s multiple options for setting the ope rating frequency. to maximize light load efficiency, the adp2230 can operate at a reduced switching frequency in psm and switch automatically to pwm as the load increases. the adp2230 can be forced to operate at 2 mhz in pwm only mode when noise considerations are more important than efficiency. the adp2230 c an also be synchronized with a 1.5 mhz to 2.5 mhz external clock via the sync pin. when using the external clock synchronization control, both buck outputs operate in phase with the applied clock signal. the adp2230 include s an internal power switch, synchronous rectifier, and compensation to minimize external part count and maximize efficiency. other key pr otection features include under voltage lockout to prevent deep battery discharge , internal soft start to prevent input current overshoot at startup , and an integrated, switched resistor, qod function that automatically discharges the output when the device is disabled . short - circuit protection and thermal overload protection circuits prevent da mage in adverse conditions. 2.2 h en1 en2 pgnd (e p ad) sync sw1 vin2 vin1 agnd c in 10 f c out1 10 f l1 2 9 ad p 2230 1 fb1 3 2.2 h sw2 c out2 10 f l2 10 fb2 8 v out1 v in v out2 5 11 on off 4 7 6 on off pwm psm/pwm 10705-001 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed b y analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2014 analog devices, inc. al l rights reserved. technical support www.analog.com
adp2230 data sheet table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 typical application circuit ............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 recommended co mponent specifications ............................... 4 absolute maximum ratings ............................................................ 5 thermal data ................................................................................ 5 thermal resistance ...................................................................... 5 esd cautio n .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 theory of operation ...................................................................... 12 overview ..................................................................................... 12 operating conditions ................................................................ 12 sync pin control schemes ...................................................... 13 features descriptions ................................................................ 13 applic ations information .............................................................. 15 setting the output voltage ........................................................ 15 selecting the inductor ................................................................ 15 selecting the input and output capacitors ............................ 16 pcb layout considerations .......................................................... 17 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 18 revision history 11/ 14 rev. 0 to rev. a changes to ordering guide .......................................................... 1 8 10 /14 revision 0: initial version rev. a | page 2 of 18
data sheet adp2230 specifications v in = v en x = 5.0 v, v out = 3.3 v, t j = ? 40c to + 125c for minimum/maximum specifications, and t a = 25c for typical specifications, unless otherwise noted. all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc). table 1 . parameter symbol test conditions/comments min typ max unit supply input voltage range v in 2.3 6.5 v quiescent current i q v sync = gnd, no load, device not switching one channel enabled 8 23 a both channels enabled 15 34 a standby current v en x = 1 v 55 a shutdown current i sd v en x = gnd, t j = ?40c to +85c 0.1 2 .5 a undervoltage lockout v in rising threshold 2.23 2.2 8 v v in falling threshold 1.96 2.05 v soft start time t ss 185 270 395 s fixed and adjustable output load regulation pwm ? v out /?i out i out = 0 ma to 800 ma 0.1 % /a line regulation ? v out /? v in v in = 2.3 v to 6.5 v, v out = 1.2 v , i out = 5 00 ma 0. 1 % /v psm rising threshold v in = 5 v, v out = 3.3 v 230 ma psm hysteresis 25 ma fixed output voltage fixed v out accuracy v in = 5 v, no load v out = 1.2 v v out _1.2v 1.168 1.2 1.220 v v out = 1.8 v v out_1. 8 v 1.748 1.8 1.851 v v out = 3.3 v v out_ 3 . 3 v 3.202 3.3 3.363 v fixed v out f b pin current 1 i fb_fixed v fb = 1.2 v 1.1 2.0 2.8 a adjustable output voltage feedback voltage v fb 0.77 4 0.8 0.81 8 v adjustable v out range v out_adj 0.8 6 v adjustable v out fb pin current i fb_adj v fb = 0.8 v 10 150 na switching characeristics on resistance v in = 5 v, i sw = 400 ma p - channel r dson_p 230 325 m n - channel r dson_n 180 275 m current limit p - channel 930 1300 1475 ma n - channel 300 500 625 ma p - channel leakage current v in = 5 v, v sw = gnd, t j = ?40c to +85c 2 a minimum on time t on - min 3 35 6 5 ns swx node discharge resistor 2 50 340 phase shift between sw1 and sw2 v sync = gnd or v sync = v in (no external clock) 180 degrees oscillator fixed pwm oscillator frequency f sw_fixed v sync = gnd or v sync = v in 1600 2000 2300 khz external clock s ynchronization range f sw_range 1 . 5 2 . 5 m hz external clock duty cycle range 20 85 % sync pin high threshold 1.3 v low threshold 0.4 v leakage current v sync = gnd or v sync = v in 0.01 1 a rev. a | page 3 of 18
adp2230 data sheet parameter symbol test conditions/comments min typ max unit enable standby logic levels 2.3 v v in 6.5 v high 1.15 v low 0.4 v hysteresis 200 mv enable precision logic levels 2.3 v v in 6.5 v operating maximum en1 v en 1 5.5 v en2 v en 2 6.5 v high enx pin rising 1.2 1.2 55 v low enx pin falling 1 1.1 v enx pin leakage current v en x = v in or gnd 0.01 1 a thermal shutdown threshold t j rising 150 c hysteresis 15 c 1 the fixed v out feedback pin current is the internal feedback voltage , 0.8 v (typical), divided by the bottom feedback resistor , typically 400 k . recommended componen t specifications t a = ?40c to +125c table 2 . parameter symbol min 1 typ max unit input and output capacitance 2 c in , c out 7 10 f capacitor equivalent series resistance (esr) esr cin , esr cout 0.001 0.01 inductance l 1.5 2.2 h 1 minimum values represent the minimum effective values of the components under the application operating conditions. to achiev e the minimum effective values, components specified as 2.2 h inductors and 10 f capacitors are recommended. 2 ensure that t he minimum input and output capacitance is greater than 7 f over the full range of operating conditions. the full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. x7r and x5r type capacitors are recommended; y5v and z5u capacitors are not recommended. rev. a | page 4 of 18
data sheet adp2230 rev. a | page 5 of 18 absolute maximum ratings table 3. parameter rating vinx, fbx, en2, sync to agnd, pgnd ?0.3 v to +7 v en1 ?0.3 v to +6 v swx to agnd, pgnd ?0.3 v to vinx operating ambient temperature range ?40c to +85c operating junction temperature range ?40c to +125c storage temperature range ?65c to +150c soldering conditions jedec j-std-020 stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. absolute maximum ratings apply individually only, not in combination. thermal data exceeding the junction temperature (t j ) limit can cause damage to the adp2230 . monitoring ambient temperature does not guarantee that t j is within the specified temperature limits. the maximum ambient temperature may require derating in applications with high power dissipation and poor thermal resistance. in applications with moderate power dissipation and low printed circuit board (pcb) thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. the junction temperature of the device is dependent on the ambient temperature, the power dissipation of the device, and the junction-to-ambient thermal resistance ( ja ) of the package. maximum t j is calculated from the ambient temperature (t a ) and power dissipation (p d ) using the formula t j = t a + ( p d ja ) (1) ja of the package is based on modeling and calculation using a 4-layer board. ja is highly dependent on the application and board layout. in applications where high maximum power dissipation exists, close attention to thermal board design is required. the value of ja can vary, depending on pcb material, layout, and environmental conditions. the specified values of ja are based on a 4-layer, 4 in. 3 in. circuit board. see jedec jesd51-7, high effective thermal conductivity test board for leaded surface mount packages , for detailed information on board construction. for more information, see an-772 application note , a design and manufacturing guide for the lead frame chip scale package (lfcsp) . jb is the junction-to-board thermal characterization parameter with units of c/w. the jb of the package is based on modeling and calculation using a 4-layer board. the jesd51-12, guidelines for reporting and using electronic package thermal information , states that thermal characterization parameters are not the same as thermal resistances. jb measures the component power flowing through multiple thermal paths rather than a single path as in junction-to-board thermal resistance ( jb ). therefore, jb thermal paths include convection from the top of the package as well as radiation from the package, factors that make jb more useful in real-world applications. maximum t j is calculated from the board temperature (t b ) and p d using the formula t j = t b + ( p d jb ) (2) for more information regarding jb , see jesd51-12 and jesd51-8, integrated circuit thermal test method environmental conditionsjunction-to-board. thermal resistance ja and jb are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. jc is a parameter for surface-mount packages with top mounted heat sinks. table 4. thermal resistance package type ja jc unit 10-lead, 3 mm 3mm lfcsp 44.6 5.45 c/w esd caution
adp2230 data sheet pin configuration and fu nction descriptions figure 2 . pin configuration table 5 . pin function descriptions pin no. mnemonic description 1 sw1 connection from mosfet power switches to the inductor for buck 1. 2 vin1 analog and power voltage input for buck 1. connect vin1 to vin2. 3 fb1 output voltage feedback for buck 1. 4 en1 precision enable for buck 1. do not leave the en1 p in floating. 5 agnd analog ground . 6 sync frequency synchronization. d r ive sync high to force the device to operate in 2 mhz fixed pwm mode. drive sync low to force the device to operate in 2 mhz psm/pwm automatic transitioning mode. apply an external clock between 1.5 mhz and 2.5 mhz to the sync pin to synchronize the adp2230 switching to the applied externa l clock. do not leave the sync p in floating. 7 en2 precision enable for buc k 2. do not leave the en2 p in floating. 8 fb2 output voltage feedback for buck 2. 9 vin2 analog and power voltage input for buck 2. connect vin2 to vin1. 10 sw2 connection from mosfet power switches to the inductor for buck 2. 11 epad e xposed pad , power ground (pgnd) . the exposed pad on the bottom of the lfcsp package enhances thermal performance and is electrically connected to pgnd inside the package. the exposed pad must be connected to the ground plane on the board for proper operation. 1 sw1 2 vin1 3 fb1 4 en1 5 agnd 10 sw2 notes 1. the exposed p ad on the bot t om of the lfcs p p ackage enhances therma l performance and is electrical l y connected t o pgnd inside the p ackage. the exposed p ad must be connected t o the ground plane on the board for proper oper a tion. 9 vin2 8 fb2 7 en2 6 sync ad p 223 0 t o p view 1 1 pgnd 10705-002 rev. a | page 6 of 18
data sheet adp2230 typical performance characteristics v in = v en x = 5.0 v, c in 1 = c in 2 = c out1 = c out2 = 10 f ( grm21br61c106ke15 ) , l1 = l2 = 2.2 h ( xfl3012 - 222meb ) , typical values are at t a = 25c, and minimum/maximum limits are guaranteed for t j = ?40c to +125c, unless otherwise noted. all limits at temperature extremes are guaranteed via correlation using standard statistical quality control (sqc). figure 3 . efficiency vs. load current, v out = 1.2 v, different input voltages figure 4 . efficiency vs. load current, v out = 3.3 v, different input voltages figure 5 . typical maximum continuous output current vs. input voltage figure 6 . load regulation, v out = 1.2 v figure 7 . load regulation, v out = 3.3 v figure 8 . psm to pwm mode transition threshold vs. input voltage 40 50 60 70 80 90 100 0.1 1 10 100 1000 efficienc y (%) load current (ma) v in = 2.5v v in = 3.5v v in = 4.5v v in = 5.5v v in = 6.5v v out = 1 . 2 v f sw = 2 m h z 10705-103 au t o mode pwm mode 50 55 60 65 70 75 80 85 90 95 100 0.1 1 10 100 1000 efficienc y (%) load current (ma) v in = 4 . 5 v v in = 5 . 5 v v in = 6 . 5 v v out = 3.3v f sw = 2 m h z 10705-104 au t o mode pwm mode 1.20 1.25 1.30 1.35 1.40 1.45 2.3 3.3 4.3 5.3 6.3 typica l maximum continuous output current (a) input vo lt age (v) v out = 1.2v v out = 1.8v v out = 3.3v 10705-105 1.170 1.175 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 1 10 100 1000 output vo lt age (v) load current (ma) v in = 2.5v v in = 3.5v v in = 4.5v v in = 5.5v v in = 6.5v v out = 1 . 2 v f sw = 2 m h z 10705-106 au t o mode pwm mode 3.26 3.27 3.28 3.29 3.30 3.31 3.32 3.33 3.34 3.35 3.36 0.1 1 10 100 1000 output vo lt age (v) load current (ma) v in = 4.5v v in = 5.5v v in = 6.5v au t o mode pwm mode v out = 3.3v f sw = 2 m h z 10705-107 10 0 12 0 14 0 16 0 18 0 20 0 22 0 24 0 26 0 28 0 2 . 3 3.0 3 . 7 4. 4 5. 1 5. 8 6. 5 l o a d curr e n t ( m a ) i n p u t v o l t a g e ( v ) v out = 1.2v rising v out = 1.8v rising v out = 3.3v rising v out = 1.2v f alling v out = 1.8v f alling v out = 3.3v f alling 10705-0 1 1 rev. a | page 7 of 18
adp2230 data sheet rev. a | page 8 of 18 figure 9. line regulation, v out = 1.2 v, different loads figure 10. line regulation, v out = 3.3 v, different loads figure 11. nmos drain-to-source on resistance (r dson ) figure 12. pmos drain-to-source on resistance (r dson ) figure 13. pmos current limit vs. inpu t voltage, different output voltages figure 14. load transient response, v out = 1.2 v, auto mode, 10 ma to 110 ma 1.14 1.16 1.18 1.20 1.22 1.24 2.3 3.3 4.3 5.3 6.3 output voltage (v) input voltage (v) i out = 1ma i out = 10ma i out = 100ma i out = 500ma i out = 800ma v out =1.2v f sw =2mhz 10705-113 10705-114 3.26 3.27 3.28 3.29 3.3 3.31 3.32 3.64.14.65.15.66.1 output volt a ge (v) input voltage (v) i out =1ma i out = 10ma i out =100ma i out =500ma i out =800ma v out = 3.3v f sw = 2mhz 0 100 200 300 400 500 600 2.3 3.3 4.3 5.3 6.3 nmos r dson input voltage (v) t a = ?40c t a = +25c t a = +125c 10705-022 0 100 200 300 400 500 600 2.3 3.3 4.3 5.3 6.3 pmos r dson input voltage (v) t a = ?40c t a = +25c t a = +125c 10705-021 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 2.3 3.3 4.3 5.3 6.3 pmos current limit (a) input voltage (v) v out = 1.2v v out = 1.8v v out = 3.3v 10705-117 1 4 load current (50ma/div) time (40s/div) output voltage (50ma/div) ac-coupled 10705-027
data sheet adp2230 rev. a | page 9 of 18 figure 15. load transient response, v out = 1.2 v, auto mode, 50 ma to 250 ma figure 16. load transient response, v out = 1.2 v, auto mode, 200 ma to 600 ma figure 17. load transient response, v out = 1.8 v, auto mode, 10 ma to 110 ma figure 18. load transient response, v out = 1.8 v, auto mode, 50 ma to 250 ma figure 19. load transient response, v out = 1.8 v, auto mode, 200 ma to 600 ma figure 20. load transient response, v out = 3.3 v, auto mode, 10 ma to 110 ma 1 4 load current (100ma/div) output voltage (50mv/div) ac-coupled time (40s/div) 10705-028 1 4 load current (200ma/div) output voltage (50mv/div) ac-coupled time (40s/div) 10705-029 1 4 load current (50ma/div) output voltage (50mv/div) ac-coupled time (40s/div) 10705-030 1 4 load current (100ma/div) output voltage (100mv/div) ac-coupled time (40s/div) 10705-031 1 4 load current (200ma/div) output voltage (100mv/div) ac-coupled time (40s/div) 10705-032 1 4 load current (50ma/div) output voltage (50mv/div) ac-coupled time (40s/div) 10705-033
adp2230 data sheet rev. a | page 10 of 18 figure 21. load transient response, v out = 3.3 v, auto mode, 50 ma to 250 ma figure 22. load transient response, v out = 3.3 v, auto mode, 200 ma to 600 ma figure 23. load transient response, v out = 1.8 v, pwm mode, 10 ma to 110 ma figure 24. load transient response, v out = 1.8 v, pwm mode, 50 ma to 250 ma figure 25. load transient response, v out = 1.8 v, pwm mode, 200 ma to 600 ma figure 26. startup, v out = 3.3 v, no load 1 4 load current (100ma/div) output voltage (100mv/div) ac-coupled time (40s/div) 10705-034 1 4 load current (100ma/div) output voltage (100mv/div) ac-coupled time (40s/div) 10705-035 1 4 load current (50ma/div) output voltage (20mv/div) ac-coupled time (40s/div) 10705-036 1 4 load current (100ma/div) output voltage (50mv/div) ac-coupled time (40s/div) 10705-037 1 4 load current (200ma/div) output voltage (100mv/div) ac-coupled time (40s/div) 10705-038 3 4 1 2 enx pin (5v/div) output voltage (5v/div) inductor current (200ma/div) swx pin (5v/div) time (40s/div) 10705-039
data sheet adp2230 rev. a | page 11 of 18 figure 27. startup, v out = 3.3 v, 800 ma figure 28. short-circuit response figure 29. typical psm operation, v out = 3.3 v, i load = 50 ma, 150 ma figure 30. typical pwm operation, v out = 3.3 v, i load = 400 ma 3 4 1 2 enx pin (5v/div) output voltage (5v/div) inductor current (500ma/div) swx pin (5v/div) time (40s/div) 10705-040 3 4 1 2 v out1 = 1.2v (2v/div) v out2 = 3.3v shorted to ground (2v/div) inductor current (500ma/div) swx pin (2v/div) time (400ns/div) 10705-041 1 3 4 swx pin (2v/div) inductor current (200ma/div) output voltage (50mv/div) ac-coupled time (2s/div) 10705-133 1 3 4 swx pin (2v/div) inductor current (200ma/div) output voltage (50mv/div) ac-coupled time (2s/div) 10705-134
adp2230 data sheet rev. a | page 12 of 18 theory of operation figure 31. internal block diagram overview the adp2230 contains two, high efficiency, step-down, dc-to- dc converters that use a proprietary, high speed, current mode, constant frequency, pwm control scheme for excellent stability and transient response. to ensure long battery life, the adp2230 also has a psm mode that reduces the switching frequency under light load conditions. the architecture ensures smooth transitions between pwm mode and psm, and maintains high efficiencies at light loads. the adp2230 operates with an input voltage between 2.3 v and 6.5 v and buck to output voltages between 0.8 v and 6 v. the adp2230 buck outputs operate out of phase to reduce the input current ripple. all versions include an internal power switch, synchronous rectifier, and internal compensation for minimal external part count. the adp2230 also includes internal protection features such as precision enable, soft start, uvlo, tsd, and short-circuit protection. the adp2230 also includes an integrated, 200 , switched resistor, quick output discharge (qod) function that automatically discharges the output when the device is disabled. the following sections describe the operating conditions, the modes of operation, and the features of the adp2230 . operating conditions input voltage the adp2230 operates with an input voltage between 2.3 v and 6.5 v. the vin1 and vin2 pins cannot be controlled separately. vin1 and vin2 must be tied together and powered from a single source. output voltage the adp2230 step-down, dc-to-dc converter is available with adjustable output voltages that can be set between 0.8 v and 6 v. the adp2230 is also available in three fixed output voltage pair options: 1.2 v/1.8 v, 1.2 v/3.3 v, or 1.8 v/3.3 v. for additional output voltage options, contact a local sales or distribution representative. slope comp oscillator control logic soft start 1.0v en1 vin2 fb2 sync 1.2v standby precision en1 vin uvlo pwm psm 0.808v 0.8v 1.2a v in v in 2.25v 0.8v 150c 135c h = pwm only l = pwm/psm thsd p_i limit n_i limit ?0.5a ? (pwm) 0a ? (psm) i min g m v comp i comp rds on kr slope comp control logic soft start vin1 sw1 pgnd fb1 pwm psm 0.808v 0.8v 1.2a v in 0.8v p_i limit n_i limit ?0.5a ? (pwm) 0a ? (psm) i min v comp i comp vto i vto i rds on kr agnd 1.0v en2 1.2v standby precision en1 fixed v out only fixed v out only sw2 10705-003 g m v in
data sheet adp2230 sync pin control sch emes there are three possible switching control schemes for the adp2230 that can be selected using the sync pin: pwm mode, psm/p wm automatic transitioning mode, and external clock synchronization. in pwm mode and psm/pwm automatic transitioning mode, the two bucks operate 180 out of phase. when using the external clock synchronization control scheme, the two bucks operate in phase . pwm mode when the sync pin is fixed high (v sync 1.3 v), the adp2230 operate s in the fixed 2 mhz pwm mode. when operating in fixed frequency pwm mode, the duty cycle of the integrated switches is adjusted to regulate the output voltage. the switching frequency is 2 mhz , typical, over all input, output, and load conditions. at the start of each oscillator cycle in pwm, the p - channel mosfet switch is turned on, putting a positive voltage across the inductor. current in the inductor increases until the current sense signal crosses the peak inductor current level that turns off the p - channel mosfet switch and turns on the n - channel mosfet synchronous rectifier. this puts a negative voltage across the inductor, causing the inductor current to decrease. the synchronous rectifier stays on until the next clock cycle. psm/pwm automatic transitioning mode when the sync pi n is fixed low (v sync 0.4 v), the adp2230 is able to automatically transition between pwm mode and psm to maintain the highest efficiency. the adp2230 operate s in fixed frequency pwm mode for medium to high load currents. if the load current falls below the psm/pwm threshold level, the converter smoothly transitions to the reduced frequency psm . the psm/pwm threshold varies with the operating conditions. t he psm/pwm transition level for various operating conditions is shown in figure 8 . the two buck converters operate independentl y and can have different psm/pwm current thresholds for the same output voltage. when the device enters psm, the adp2230 switches only when necessary to maintain the output voltage within regulation. when the output voltage falls below the lower regulation threshold, the adp2230 enter s pwm mode for a few oscillat or cycles until the output voltage reaches the upper regulation threshold. when it reaches the upper threshold, the adp2230 enter s sleep mode and wait s for the output voltage to fall below the l ower regulation threshold. during the wait time between the bursts, both power switches are off to minimize quiescent current, and the output capacitor supplies the entire load current. due to the psm architecture, the output voltage ripple in this mode is larger than the ripple in the pwm mode of operation. figure 29 shows the typical operation in psm mode. external clock synchronization when a 1.5 mhz to 2.5 mhz external clock is applied to the sync p in, the adp2230 automatically detect s the rising edge of the first clock and synchronize s to the external clock. if the device is synchronized to an external clock, the two bucks operate in phase, psm is disabled , and the device is forced to operate in pwm mode only. features descriptions precision enable the adp2230 has two enable inputs, en1 and en2, that allow each of the buck outputs to be enabled and shut down inde - pendently. the enable circuits of the adp2230 minimiz e the input current during shutdown and simultaneously provide precision enable thresholds. when the enable input voltages are below 0 .4 v, the regulators are in shutdown mode. when both buck converters are in shutdown mode, the supply current is 0.1 a ( t ypical ) . as the enable input voltages rise above the standby enable threshold of 1.15 v (minimum), the internal bias currents and voltages are activated, turning on the precision enable circuitry. this allows the precision enable circuitry to accurately de tect when the en x pin voltage exceeds the precision enable rising threshold of 1.2 v (maximum). due to device constraints, en1 and en2 have different operating maximums. en2 has a 6 .5 v operating maximum and can be directly connected to vin x for any applic ation. en1 has a 5.5 v operating maximum and cannot be directly connected to vin x f or applications where v in is greater than 5.5 v . connect a resistor divider from vin x to en1 to reduce the voltage applied to the en1 pin to 5.5 v or less. quick output discharg e the adp2230 includes an internal , 200 discharge resistor on the sw x p in that forces the output voltage to zero when the buck is disabled. this ensures that the output of the buck is a lways in a well defined state. output short - circuit protection the adp2230 include s frequency foldback to prevent output current runaway on a hard short. when the voltage at the feedback pin ( f bx ) falls below 0.3 v, indicating the possibility of a hard short at the output, the sw itching frequency is reduced to half of the internal oscillator frequency. the reduction in the switching frequency provides more time for the inductor to discharge, preventing a runaway of output current. underv oltage lockout to protect against battery discharge, an undervoltage lockout (uvlo) circuit is incorporated into the adp2230 . when the input voltage drops below the uvlo threshold, the adp2230 shuts down, and both power switches and both synchronous rectifiers turn off. if en1 and en2 are logic high , when the input voltage rises above the uvlo threshold, the soft start periods are initiated and the two buck converters are enabled. rev. a | page 13 of 18
adp2230 data sheet thermal shutdown in the event that the junction temperature of the adp2230 rises above 150c, the thermal shutdown protection circuit turns off the regulator. extreme junction temperature can be the result of high current operation, poor circuit board design, and/or high ambient temperature. a 15c hysteresis is i ncluded in the protection circuit so that when a thermal shutdown occurs, the device does not return to normal operation until the on - chip temperature drops below 135 c. upon exiting thermal shutdown, the soft start sequences are initiated. soft start the adp2230 has an internal soft start function that ramps the output voltage in a controlled manner upon startup, thereby limiting the inrush current. this prevents possible input voltage drops whe n a battery or a high impedance power source is connected to the input of the converter. typical soft start time is 350 s. the adp2230 is also capable of starting up into a precharged output ca pacitor. if soft start is invoked when the output capacitor charge is greater than zero, the device delays the start of switching until the internal soft start ramp reaches the corresponding fb voltage. this feature prevents discharging the output capacito r at the beginning of soft start. current limit the adp2230 has protection circuitry that limits the direction and amount of current that flows through the power switch and synchronous rectifier , cycle by cycle. the positive current limit of 1300 ma ( typical ) on the power switch limits the amount of current that can flow from the input to the output. in pwm, the adp2230 also has a negative current limit of 500 ma ( typical ) , on the synchronous re ctifier that prevents the inductor current from reversing direction and flowing out of the load. 100% duty cycle the adp2230 enter s and exit s 100% duty cycle smoothly. the control loop seeks the next clock cycle while the high - side switch is engaged. when this occurs, the clock signal is masked , and the pmos remains on. when the input voltage increases, the internal v comp node decreases its sig nal to the control loop; thus, the device stops skipping clock cycles and exits 100% duty cycle. rev. a | page 14 of 18
data sheet adp2230 rev. a | page 15 of 18 applications information the adp2230 is designed with a high 1.5 mhz to 2.5 mhz operating frequency that enables the use of small chip inductors and capacitors that are ideal for use in applications with solution size constraints. the external component selection for the adp2230 application circuit is also driven by the input and output operating requirements. compatible components for the application circuits in figure 32 and figure 33 are identified using the recommended inductors in table 6 and selection guides in the following sections. figure 32. typical application circuit fixed output voltage figure 33. typical application circuit adjustable output voltage setting the output voltage the adp2230 is available with 1.2 v/1.8 v, 1.2 v/3.3 v, or 1.8 v/3.3 v fixed output voltage pairs. for these options, the output voltage is set by an internal resistive feedback divider, and no external resistors are necessary to set the output, as shown in figure 32. the adp2230 is available with adjustable output voltage pairs and can be configured for output voltages between 0.8 v and 6 v. the output voltage is set by a resistor voltage divider, r1 fbx , from the output voltage (v out ) to the 0.8 v feedback input at fbx and r2 fbx from fbx to ground (see figure 33). use the following equation to determine r1 and r2 for the desired v out : fb out v r2 r1 v ? ? ? ? ? ? ? ?? 1 (3) where v fb = 0.8 v, typical. selecting the inductor the adp2230 is designed for optimal performance with 2.2 h inductors that have favorable saturation currents and lower dc resistances (dcr) for their given physical size. other inductor values are not recommended. to ensure stable and efficient performance with the adp2230 , select a compatible inductor with a sufficient current rating, saturation current, and low dcr. the specifications and value of the selected inductor affect efficiency, output ripple, transient response, and the transition level between psm/pwm. suggested inductors are shown in table 6. the saturation current of the selected inductor must be greater than the maximum peak inductor current, i pk , of the applica- tion. the maximum peak inductor current is the maximum load current plus half the inductor ripple current determined by the following equation: ? ? ? ? ? ? ? ? ? 2 )( l max load pk i ii (4) where i l is the ripple current of the inductor. the ripple current can be calculated as follows: ? ? ? ? ? ? ? ? ?? ? ?? in out sw out l v v lf v i 1 (5) where: f sw is the switching frequency in mhz (2 mhz, typical). l is the inductor value. the largest ripple current, i l , occurs at the maximum input voltage. 2.2 h en1 en2 pgnd (epad) sync sw1 vin2 vin1 agnd c in 10f c out1 10f l1 2 9 adp2230/ adp2231 1 fb1 3 2.2 h sw2 c out2 10f l2 10 fb2 8 v out1 = 1.2v v in = 6.0v v out2 = 1.8v 5 11 on off 4 7 6 on off pwm psm/pwm 10705-004 2.2 h en1 en2 pgnd (epad) sync sw1 vin2 vin1 agnd c in 10f c out1 10f l1 2 9 1 fb1 3 2.2 h sw2 c out2 10f l2 10 fb2 8 v out1 = 3.3v v in = 6.0v v out2 = 1.8v 5 11 on off 4 7 6 on off pwm psm/pwm r1 fb1 r2 fb1 r1 fb2 r2 fb2 adp2230/ adp2231 10705-005
adp2230 data sheet table 6 . suggested inductors manufacturer part number inductance (h) dcr (m ? ) typ current rating (a) saturation current (a) size (l w h) (mm) package tdk mlp2016s2r2m 2.2 20% 110 1.20 n/a 2.00 1.60 1.00 0806 mlp2520s2r2s 2.2 20% 110 1.20 1.20 2.50 2.00 1.00 1008 vlf252012mt - 2r2m 2.2 20% 57 1.67 1.04 2.50 2.00 1.00 1008 vlf302510mt - 2r2m 2.2 20% 70 1.23 1.37 3.00 2.50 1.00 n/a vlf302515mt - 2r2m 2.2 20% 42 2.71 1.57 3.00 2.50 1.40 n/a murata lqm2hpn2r2mg0 2.2 20% 80 1.30 n/a 2.50 2.00 0.90 1008 lqh32pn2r2nnc 2.2 30% 64 1.85 n/a 3.20 2.50 1.55 1210 wurth 74479787222 2.2 20% 80 1.50 0.70 2.50 2.00 1.00 1008 7440430022 2.2 30% 23 2.50 2.35 4.80 48.0 2.80 n/a taiyo yuden brc2012t2r2md 2.2 20% 110 1.00 1.10 2.00 1.25 1.40 0805 toko mdt2520 - cr2r2m 2.2 20% 90 1.35 n/a 2.50 2.00 1.00 1008 dem2810c (1224as - h - 2r2m) 2.2 20% 85 1.10 1.40 3.20 3.00 1.00 n/a dem2815c (1226as - h - 2r2m) 2.2 20% 43 1.40 2.20 3.20 3.00 1.50 n/a coilcraft xpl2010 - 222 2.2 20% 156 0.9 6 0.94 1.9 0 2.00 1.00 n/a xfl3010 - 222 2.2 20% 111 1.0 0.94 3.00 3.00 1.00 n/a xfl3012 - 222 2.2 20% 81 1. 40 1.00 3.00 3.00 1.3 0 1212 1 n/a means not applicable. selecting the input and output capacitor s the adp2230 is designed for optimal performance with 10 f capacitors. use any size , good quality , low esr, x5r or x7r ceramic capacitors with the adp2230 , as long as they meet the capacitance and voltage requirements of the application. capacitors less than 10 f are not recommended. input capacitor the adp2230 is designed to operate with a single 10 f input capacitor ( c in ) . the input capacitor must be able to support the maximum input operating voltage and the maximum rms input current. place the input capacitor as close as possible to the vin x pins to reduce input voltage ripple. select an input capacitor capable of withstanding the rms input current for the maximum continuous load current in the application using the following equation: ( ) in out in out max out rms v v v v i i ? ) ( (6) the input capacitor reduces the input voltage ripple caused by the switch currents on the vi nx pin and reduces the cir cuit sensitivity to the pcb layout, especially when long input traces or high source impedance are encountered . o utput capacitor the adp2230 require s two 10 f capacitors, c out1 and c out2 , with one capacitor on each buck output. the output capacitor selection affects both the output voltage ripple ( v out ) and the stability of the control loop. the adp2230 is designed for operation with small, space saving ceramic capacitors, but function with most commonly used capacitors as long as care is taken to calculate the effective esr value. capacitors with low esr values produce the lowest output voltage ripple . a capacitor with an esr between 0.001 and 0 .01 ? is recommended to ensure stability of the adp2230 . to determine the maximum esr for a given v out , use the following equation: l out max c i v esr out ? ? < ) ( (7) w here v out is the peak - to - peak ou tput voltage ripple as calculated in equation 8 . the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor esr plus the voltage ripple caused by charging and discharging the output capacitor. the output voltage rippl e is determined by the following equation: v out i l ( esr c out + 1/(8 c out f sw )) (8) where: esr c out is the esr of the chosen capacitor. i l is the ripple current of the inductor calculated in equation 7 . the largest voltage ripple occurs at the highest input voltage. at light load currents, if sync is set low , the converter operates in ps m, and the output voltage ripple increases. to improve the t ransient response of the adp2230 , increas e the value of c out . capacitors less than 10 f are not recommended. rev. a | page 16 of 18
data sheet adp2230 rev. a | page 17 of 18 pcb layout considerations for high efficiency, good regulation, and stability with the adp2230 , a well designed pcb is required. poor layout can affect the adp2230 buck performance, causing electromagnetic interference (emi), poor electromagnetic compatibility (emc), ground bounce, and voltage losses. improve heat dissipation from the package by increasing the amount of copper attached to the pins of the adp2230 . use the following guidelines when designing pcbs: ? keep the low esr input and output capacitors, cin and cout, and the inductors, l1 and l2, as close as possible to the adp2230 . avoid long trace lengths from the device to the capacitors that add series inductance and may cause instability or increased ripple. ? route the output voltage path away from the inductor and swx node to minimize noise and magnetic interference. ? keep high current traces as short and as wide as possible. ? avoid routing high impedance traces near any node connected to swx or near the inductor to prevent radiated noise injection. ? use a ground plane with several vias connected to the component side ground to reduce noise interference on sensitive circuit nodes. ? the use of 0402 or 0603 capacitors achieves the smallest possible footprint solution where board area is limited. figure 34. pcb layout, top figure 35. pcb layout, bottom 10705-009 10705-008
adp2230 data sheet rev. a | page 18 of 18 outline dimensions figure 36. 10-lead lead frame chip scale package [lfcsp_wd] 3 mm 3 mm body, very very thin, dual lead (cp-10-9) dimensions shown in millimeters ordering guide model 1 buck 1 output voltage (v) 2 buck 2 output voltage (v) 2 temperature range package description package option branding ADP2230ACPZ-1218R7 1.2 1.8 C40c to +85c 10-lead lfcsp_wd cp-10-9 lj3 adp2230acpz-1233r7 1.2 3.3 C40c to +85c 10-lead lfcsp_wd cp-10-9 lm3 adp2230acpz-1833r7 1.8 3.3 C40c to +85c 10-lead lfcsp_wd cp-10-9 lmk adp2230acpz-r7 adjustable adjustable C40 c to +85c 10-lead lfcsp_wd cp-10-9 lmq adp2230cp-evalz evaluation board with adjustable output voltage option 1 z = rohs compliant part. 2 for additional output voltage options, contact a local sales or distribution representative. 2.48 2.38 2.23 0.50 0.40 0.30 10 1 6 5 0.30 0.25 0.20 pin 1 index area seating plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed pad 3.10 3.00 sq 2.90 p i n 1 i n d i c a t o r ( r 0 . 1 5 ) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 0 2-05-2013-c top view bottom view 0.20 min ?2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d10705-0-11/14(a)

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